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Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors My library Help Advanced Book Search. Cache and Interconnect Architectures in Multiprocessors. Michel Dubois , Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems Eg. Sequent's Symmetry, Encore's Multimax are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop. Selected pages Title Page. Contents VirtualAddress Caches in Multiprocessors. Performance of Symmetry Multiprocessor System. Predicting the Performance of Shared Multiprocessor Caches. Thakkar Snippet view - Thakkar No preview available - VirtualAddress Caches in Multiprocessors. Cache and interconnect architectures in multiprocessors Michel Dubois , S.
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